Rapid Modeling and Analysis Framework for Full-Chip/Package/Board Layout Automation

Rapid and accurate layout modeling and analysis at a scale as large as full-chip, complete package and whole board is one of the key enablers to the success of machine generated physical layout in fast CPU run time. Existing layout tools lack such a capability, which has resulted in frequent layout failure and time intensive manual correction of the layout. In this work, PI Jiao has developed algorithms and software for rapid and first-principle-accurate full-chip/package/board layout modeling and analysis, and used such a capability to guide layout synthesis in a fast turnaround time.