Xilinx RF System-on-Chip (RFSoC) 100 Gigabit Ethernet Loop-back Demonstration
Abstract:
The ability to move high quantities of instantaneous RF bandwidth data to or from transmitter or receiver processing hardware is paramount to realizing the value of modern RF system-on-chips (RFSoCs), which are staples of many software-defined radio applications. However, practically establishing, initiating, and verifying a working 100 Gigabit Ethernet (100GigE) construction in a high-speed RF construct is not trivial. This report describes practical procedures to implement and observe a 100GigE loop-back demonstration on the Xilinx Generation 1 RFSoC. The authors first discuss the proper initialization of 100GigE hardware and its interconnected RF transmit and receive architecture. Then demonstrated are several working 100GigE loop-back configurations, including single and dual analog-to-Ethernet-to-digital transmissions. Output artifacts are observed on external oscilloscopes, and transmission latency attributed to 100GigE is measured.