Iris Recognition Using Parallel and Sequential Logic in a Reconfigurable Logic Device

Biometrics technologies have grown considerably in recent years with better computing and an expanding realm in which these tools are deployed. Among these, iris recognition demonstrates superior performance as a biometric, perhaps far exceeding the standard fingerprint recognition of past decades. Unfortunately, iris recognition is very computationally intensive, requiring near state-of-the-art traditional processing methods. Because of the complexity of iris recognition systems, many portable iris scanners are bulky, cumbersome and very expensive, often requiring laptop computers to carry out the computations. This is due to a reliance on sequential processing, the manner of computing we see in a typical personal computer. However, there is an alternative with parallel processing using multicore processors, field-programmable gate arrays FPGAs or application specific integrated circuits ASICs. These devices can speed algorithms through parallel processing. Taking the algorithm developed by Dr. Robert Ives et al. of the United States Naval Academy for iris recognition, parallelizable parts of the algorithm can be translated for parallel processing. A parallel version of the algorithm may be substantially faster and physically much smaller implemented. This implementation is placed into an FPGA system in order to evaluate the performance of specific parts of the algorithm converted from sequential C code to parallel hardware logic with respect to speed and hardware footprint. Additionally, this project seeks to evaluate the feasibility of an entirely embedded iris recognition system comprised of both sequential C software and parallel hardware on a single chip and a discrete memory module. The resulting hardware is shown to be between 10 and 1000 times faster than current methods while being entirely embedded and independent of a host system for processing.