Field Programmable Gate Array Based Global Communication Channel for Digital Signal Processor Chips

reportActive / Technical Report | Accession Number: ADA471400 | Open PDF

Abstract:

An apparatus comprising a host digital signal processor DSP, at least one field programmable gate array FPGA in communication with the host DSP for receiving a digital signal from the host DSP, and at least one non-host DSP in communication with the at least one FPGA for receiving the digital signal.

Author(s):
Dutton, C. R.
Author Organization(s):
DEPARTMENT OF THE NAVY WASHINGTON DC
Descriptive Note:
Patent application, filed 11 Jul 2005
Pagination:
0012

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
PAT-APPL-11 183 313
Monitor Series:
NAVEXOS
 Subject Terms
Joint Capability Areas:
JCA_6.1.1_Wired Transmission; JCA_6.1_Information Transport; JCA_6_Net Centric
Modernization Areas:
Microelectronics
Communities of Interest:
Advanced Electronics
Descriptor(s):
*SIGNAL PROCESSING, *FIELD PROGRAMMABLE GATE ARRAYS, DIGITAL SYSTEMS, PATENT APPLICATIONS, NETWORKS, CHIPS(ELECTRONICS), CONFIGURATIONS, INVENTIONS
Field(s)/Group(s):
Electrical and Electronic Equipment, Computer Programming and Software, Computer Systems
Keyword(s):
*DSPS(DIGITAL SIGNAL PROCESSORS)
Report Date:
2005 Jul 11
Creation Date:
2007 Sep 12