Extending Cache Coherence to Support Thread-Level Data Speculation on a Single Chip and Beyond

Thread Level Data Speculation TLDS is a technique which enables the optimistic parallelization of applications despite ambiguous data dependences between the resulting threads. Although TLDS is mostly managed by software, hardware provides two key pieces of functionality 1 detecting dependence violations, and 2 buffering speculative side effects until they can be safely committed to memory. To provide this functionality we present an extension to invalidation based cache coherence which is both scalable and has a minimal impact on hardware complexity. We explore the design space in depth and find that our baseline architecture is sufficient to exploit speculative parallelism.