VHSIC Hardware Description Language (VHDL) Benchmark Suite

This report documents changes and additions made to the VHDL benchmark Suite released in October 1989 WRDC-TR-89-5046. Each benchmark is designed to test one or more of a set of 71 VHDL language features in terms of the limitations of users or vendors system architecture, operating system, and VHDL toolset. These limitations could include CPU time and amount of memory required to simulated a test. Examples of language feature tests are the maximum number of signal declarations allowed in an architecture or the maximum size number of characters of a process label.