A Single-Phase Clocked NOR/NOR CMOS Programmable Sequential Array Structure

A static CMOS Programmable Sequential Array PSA structure is presented, which uses a precharge CMOS NORNOR logic structure to implement combinational logic. It is fast, it consumes no static power, and it imposes no limits on the number of input terms. Only one input clock is required while additional clocks are generated by the PSA structure. Static latches are added to the output. Results will remain unchanged with the absence of a high clock signal. This single-phase clocking technique, with statistically latched outputs, permits this proposed PSA to be used for many different system overall timing strategies. The proposed methodology has been implemented with MOSIS scalable design rules and has been adapted into the Berkeley VLSI CAD tool system--MPLAs tiling format. An automatically generated example is given.