A Pad Router for the Monterey Silicon Compiler

reportActive / Technical Report | Accession Number: ADA196522 | Open PDF

Abstract:

A two layer pad router is developed for the Monterey Silicon Compiler. Features include an improved pad placement routine that extracts information from the internal layout to minimize chip area and wiring lengths, and a track allocation algorithm that minimizes the use of polysilicon during net layout. The routers performance was compared to that of the MacPitts Silicon Compiler with four distinct circuits. The Monterey pad router layouts were 5 to 25 faster, and 10 to 15 smaller than those produced by MacPitts.

Author(s):
Rexach, Carlos F.
Author Organization(s):
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Descriptive Note:
Master's thesis
Pagination:
0182

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Monitor Series:
NPS
 Subject Terms
Joint Capability Areas:
JCA_6.1.3_Switching and Routing; JCA_6_Net Centric; JCA_6.1_Information Transport; JCA_5_Command and Control; JCA_5.3_Planning; JCA_1_Force Support; JCA_1.3_Human Capital Management; JCA_1.3.2_Personnel Management; JCA_4.6_Engineering; JCA_1.2.5_Lessons Learned; JCA_1.2_Force Preparation; JCA_1.2.3_Educating; JCA_5.4_Decide
Modernization Areas:
Microelectronics
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*COMPUTER AIDED MANUFACTURING, *ROUTING, *CHIPS(ELECTRONICS), COMPILERS, SILICON, ALLOCATIONS, THESES, COMPUTER AIDED DESIGN, ALGORITHMS, INTERNAL
Field(s)/Group(s):
Computer Hardware, Manufacturing and Industrial Engineering and Control of Production Systems, Machinery and Tools
Keyword(s):
*ROUTERS, PAD ROUTERS, VLSI(VERY LARGE SCALE INTEGRATION)
Report Date:
1988 Mar 01