Simulation of Fault Tolerance in a Hypercube Arrangement of Discrete Processors.

The purpose of this study was to implement a technique for fault-tolerant parallel computation on the Intel Corporations Hypercube computer. This work was motivated by the recent progress in parallel computation and neural network techniques. This study focuses on the implementation of one particular type of parallel processing architecture on the Intel Hypercube. The architecture in question is known as the cube-connected cycle CCC. This architecture is used as a basis for a reconfiguration scheme known as reconfigurable cube-connected cycles. The aim of this reconfiguration is to build a parallel computing system with fault tolerance capability. Implementation of this technique on the Intel Hypercube was by simulation. The loading of only part of the hypercube available nodes, holding the remaining nodes in reserve was accomplished, followed by a simulation of the replacement of a deactivated node with a spare node. Conclusions are reached regarding the suitability of the Intel machine for fault tolerance experiments versus the rapid computation for which it was designed. Recommendations are made regarding the next logical steps in continuation of the work presented in this study.