Development of a Butterfly (Trademark) Multiprocessor Test Bed: The Butterfly Switch.

This technical report is the third in a series that describes progress on the development of a 128-processor Butterfly TM testbed. As part of the testbed effort, we have developed the Butterfly Switch chip a single-chip implementation of the algorithm used to route messages through the Butterfly Switch. In conjunction with the switch chip, we have developed the packaging and a printed circuit board needed to incorporate the switch chip into Butterfly systems. This report first reviews the design of the Butterfly Switch and then describes the Butterfly switch chip and associated packaging. It has been nearly a decade since BBN began studying the idea of using the Butterfly Switch as the basis for a parallel processor system. The design of the switch was first presented in BBN Report No. 3501, and updated in Report No. 4098. The Butterfly switch is one of many multiprocessor interconnection networks that have been proposed and studied in recent years.