Programming Processor Interconnection Structures

Programming Processor Interconnection Structures

Active / Technical Report | Accession Number: ADA109294 |

Abstract:

Parallel computer architecture complicates the already difficult task of parallel programming in many ways, e.g., by a rigid interconnection structure, addressing complexity, and the shape and size mismatches. The CHiP computer is a new architecture that reduces these complications by permitting the processor interconnection structure to be programmed. This new kind of programming is explained. Algorithms are presented for several interconnection patterns including the torus and the complete binary tree and general embedding strategies are identified. Author

Author(s):

Snyder, Lawrence

Author Organization(s):

PURDUE UNIV LAFAYETTE IN DEPT OF COMPUTER SCIENCES

Descriptive Note:

Interim technical rept.

Supplementary Note:

DOI: 10.21236/ADA109294

Pagination:

0028

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:

Approved For Public Release

RECORD

Collection: TR

Identifying Numbers

Report Number(s):

CSD-TR-381

Contract/Grant Number(s):

N00014-80-K-0816, N00014-80-K-0360

Monitor Series:

ONR

Subject Terms

Joint Capability Areas:

JCA_6.1.3_Switching and Routing; JCA_6.1_Information Transport; JCA_6_Net Centric; JCA_5_Command and Control; JCA_1_Force Support; JCA_1.2_Force Preparation

Modernization Areas:

AI and Machine Learning

Communities of Interest:

Air Platforms

Descriptor(s):

*COMPUTER COMMUNICATIONS, *COMPUTER ARCHITECTURE, *MULTIPROCESSORS, MICROPROCESSORS, PARALLEL PROCESSORS, NODES, MICROELECTRONICS, CIRCUIT INTERCONNECTIONS, ROUTING, MATRICES(CIRCUITS), ADDRESSING

Field(s)/Group(s):

Computer Hardware

Keyword(s):

CHiP(Configurable Highly Parallel), CHIP computer, Trees(Mathematics), WUNRSRO100

Report Date:

1981 Oct 01