Design Considerations and Trade-Offs in MOS/LSI.

In order to be cost-effective, digital circuits implemented in MOS large scale integration LSI are designed with close regard to optimality. Three criteria - power dissipation, chip area cost, and speed - are balanced to produce a final circuit. Current practices involve a significant amount of simulation to determine the most satisfactory trade-offs. This project is concerned with the prediction of optimal values of certain design parameters for a given function of the above three criteria. This paper first develops a simplified model for MOSLSI circuits. Using this model, equations are derived for circuit speed, power dissipation, and area. These equations are expressed as functions of the channel dimensions of the MOS transistors and of the degree of pipelining of the circuit. These three equations, and their pairwise products, are then optimized. The relationships between the equations and the parameters are examined. The effects and trade-offs of particular design choices are described. Author