CLEAR: Cross-Layer Exploration for Architecting Resilience

Cheng, Eric; Mirkhani, Shahrzad; Szafaryn, Lukasz G.; Cher, Chen-yong; Cho, Hyungmin; Skadron, Kevin; Stan, Mircea R.; Lilja, Klas; Abraham, Jacob A.; Bose, Pradip; Mitra, Subhasish

CLEAR: Cross-Layer Exploration for Architecting Resilience

Active / Technical Report | Accession Number: AD1041979 |

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Abstract:

CLEAR is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures achieve desired resilience targets at minimal costsenergy, power, execution time, area by combining resilience techniques across various layers of the system stack circuit, logic, architecture, software, algorithm. CLEAR automatically and systematically explores the large space of techniques and their combinations 586 cross-layer combinations in this paper, derives cost-effective solutions, and provides guidelines for designing new techniques. Carefully optimized combinations of circuit-level hardening, logic-level parity checking, and micro-architectural recovery provide highly cost-effective soft error resilience for general-purpose processor cores. 50x silent data corruption rate improvement is achieved at 2.1 energy cost for out-of-order 6.1 for in-order cores, with no speed impact. Selective circuit-level hardening alone, guided by thorough application benchmark analysis, also provides cost-effective solutions 1 additional energy cost for the same 50x improvement.

Author Organization(s):

Stanford University Stanford United States

Descriptive Note:

Conference Paper

Supplementary Note:

Annual GOMACTech Conference (GOMACTech 17) (42nd), 20 Mar 2017, 23 Mar 2017, See also AD1034309 - Presented at the Annual Gomactech Conference (GOMACTech 17) (42nd) Government Microcircuit Applications And Critical Technology Conference. Technologies For Secure Spectrum Access From Dc To Light held in Reno, Nevada on 20-23 March 2017.

Pagination:

0004

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:

Approved For Public Release

Distribution Statement:

Approved For Public Release;

RECORD

Collection: TR

Subject Terms

Joint Capability Areas:

JCA_5.3_Planning; JCA_5_Command and Control; JCA_6_Net Centric; JCA_1.2_Force Preparation; JCA_1_Force Support; JCA_6.1.3_Switching and Routing; JCA_6.1_Information Transport; JCA_1.2.1_Training; JCA_6.3.3_Spectrum Management

Modernization Areas:

Microelectronics

Communities of Interest:

Engineered Resilient Systems

Descriptor(s):

digital systems, reliability, algorithms, complex systems, energy, computer programs, circuits, resilience, FAILURE (ELECTRONICS), cost effectiveness, costs, fault tolerance, computing system architectures, computer architecture

Field(s)/Group(s):

Computer Hardware

Keyword(s):

clear(Cross Layer Exploration for Architecting Resilience)

Report Date:

2017 Mar 01

Creation Date:

2017 Dec 05