Cross-Layer Resilience Exploration

reportActive / Technical Report | Accession Number: AD1023378 | Open PDF

Abstract:

Low-cost fault tolerance requires careful combination of fault tolerance techniques across all levels of the system stack. We describe a systematic framework, applicable to simple and complex cores as well as specialized accelerators, to explore this cross-layer design space in terms of area, power, and performance costs, and present illustrative results.

Author(s):
Cheng, Eric ; Cho, Hyungmin ; Mitra, Subhasish ; Szafaryn, Lukasz G. ; Skadron, Kevin ; Stan, Mircea ; Cher, Chen-yong ; Mirkhani, Shahrzad ; Abraham, Jacob A.
Author Organization(s):
Stanford University Stanford United States
Descriptive Note:
Conference Paper
Supplementary Note:
Government Microcircuit Applications and Critical Technology Conference (40th) (GOMACTech-15) , 23 Mar 2015, 26 Mar 2015, See also AD1022502,
Pagination:
0004

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release;

RECORD

Collection: TR
Identifying Numbers
Contract/Grant Number(s):
HR0011-13-C-0022
 Subject Terms
Joint Capability Areas:
JCA_5.3_Planning; JCA_5_Command and Control; JCA_1.2_Force Preparation; JCA_1_Force Support; JCA_6.1.3_Switching and Routing; JCA_3.2_Engagement; JCA_3_Force Application
Modernization Areas:
Microelectronics
Communities of Interest:
Engineered Resilient Systems
Descriptor(s):
fault tolerance, reliability, RADIATION HARDENING, algorithms, circuits, resilience, compilers, vulnerability, recovery
Field(s)/Group(s):
Electrical and Electronic Equipment
Keyword(s):
cross layer resilience, soft errors, system stack, single event upsets, flip flop vulnerability, logic parity, sihft(software implemented hardware fault tolerance), abft(algorithm based fault tolerance)
Report Date:
2015 Mar 31
Creation Date:
2015 Mar 31