Transmuter a Reconfigurable Computer

This report presents the final state of the DARPA Software Defined Hardware (SDH) program named Transmuter. The goal of SDH is to build a runtime-reconfigurable hardware and software that enables near ASIC performance without sacrificing programmability. Transmuter is a fast reconfigurable design consisting of a sea of tiny, in-order cores connected through a two-level cache-crossbar hierarchy to high-bandwidth off-chip memory. Transmuter v1.0 was fabricated in 28 nm CMOS and occupies 12 mm2. Across kernels, median energy-efficiency improvements of 11.6 and37.2 are achieved versus the CPU and GPU, respectively. The RTL design of the system has been validated on an FPGA prototype and is ready for transition to several potential future programs. The software met the programmability goals of the program and is available in several open-source software releases.