Mixed-Mode Circuits For Extreme Speed and Precision

reportActive / Technical Report | Accesssion Number: AD1226266 | Open PDF

Abstract:

The aim of this project, in the phase 2, is to develop a high-frequency phase-locked loop circuit in GF 45nm RFSOI technology with a phase noise specification that is required to be lower than -100 and -120 dBc/Hz at 100 kHz and 1 MHz offset frequencies, respectively. A prototype circuit was designed and fabricated in the target technology, exhibiting -121 and -128 dBc/Hz, respectively, based on lab measurements. Some circuits for characterizing the technology were developed as well.

Author(s):
Tajalli, Armin
Author Organization(s):
UTAH UNIV SALT LAKE CITY
Funding Organization(s):
AIR FORCE RESEARCH LAB WRIGHT-PATTERSON AFB OH, WRIGHT PATTERSON AIR FORCE BASE, OH
Document Type:
Technical Report/Final Report
Publication Date:
2024 Apr 17
Pagination:
97

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution Code:
A - Approved For Public Release
Distribution Statement: Public Release.
Copyright: Not Copyrighted

RECORD

Collection: TRECMS
Subject Terms
Keyword(s):
RF mixed-mode devices, RF frontends, broadband mixed-mode circuits, phase-locked loop, SiGe BiCMOS circuits, low phasenoise oscillators, rf(radio frequency)
Subject Categories:
Electrotechnology and Fluidics
Creation Date:
2024 Apr 25
Update Date:
2024 May 01