An Automatic Intellectual Property (IP) Generator for Customizable Field Programmable Gate Array (FPGA) Architectures
Abstract:
This project describes the development of an automatic IP generator for customizable FPGA architectures, as key element to kick-start a viable open-source System-On-Chips (SoC) ecosystem as defined in DARPA ERI POSH program, Technical Area 2 (TA-2). Such tool can significantly reduce the development and research time required to embed custom FPGAs into SoCs, especially for DoD applications, such as next-generation unmanned aerial vehicles and advanced wireless/ Software Defined Radio (SDR) designs.
Security Markings
DOCUMENT & CONTEXTUAL SUMMARY
Distribution Code:
A - Approved For Public Release
Distribution Statement: Public Release.
Copyright: Not Copyrighted
RECORD
Collection: TRECMS