A Tensorflow to Real-Time Machine Learning (RTML) Compiler
Abstract:
This project developed techniques for compiling deep learning models to silicon hardware with a computation mapping and schedule. The key results are (i) a novel technique to effect mapping and scheduling of deep learning model computations on hardware, and (ii) a proof-of-concept energy-efficient hardware implementation capable of both training and inference tasks.
Security Markings
DOCUMENT & CONTEXTUAL SUMMARY
Distribution Code:
A - Approved For Public Release
Distribution Statement: Public Release
RECORD
Collection: TRECMS