Vertical CMOS Logic: FY21 Advanced Devices Technical Investment Program

Pushing data-intensive applications such as artificial intelligence and machine learning to edge nodes requires increasing performance and reducing power of digital CMOS logic as well as increasing the number of available arithmetic logic units and cache memory capacity. To realize such improvements, the vision of the vertical CMOS logic concept is to turn the entire CMOS transistor logic layer on its side to build vertical logical gates composed of six or more vertically oriented transistors monolithically fabricated from a single silicon nanowire. Akin to skyscrapers in a densely populated city, the vertical logic scheme will enable an enormous increase in computational resources while at the same time improving circuit-level performance and power. FY21 was the first year of an anticipated three-year effort. The scope of the effort for FY21 was adjusted from the original proposal to reflect the awarded funding. This report describes progress on the three revised tasks. Section 1 provides an introduction to the technology concept. Section 2 covers logic set functionality and calculations of energy efficiency. Section 3 explores potential fabrication process flows. Section 4 describes progress toward selective epitaxial nanowire growth. Section 5 is a brief summary and outlook toward FY22.