A Quaternary Logic Encoder-Decoder Circuit Design Using CMOS,

Freitas, D. A.; Current, K. W.

A Quaternary Logic Encoder-Decoder Circuit Design Using CMOS,

Active / Technical Report | Accession Number: ADP002351 |

Abstract:

A binary-to-quaternary encoder and quaternary-to-binary decoder circuit pair is described as designed in a 5-volt CMOS technology. These circuits communicate with logical currents. Using model parameter values for a standard 5-micron polysilicon gate process technology and 10 microamp logical currents, we have simulated propagation delays of about 20 ns from binary encoder input to binary decoder output. With the encoder using scaled-up logical currents and driving a 100 pF load on the decoder input to simulate communication between chips, we observe simulated worst-case delays of about 35ns. Author

Author(s):

Freitas, D. A. ; Current, K. W.

Author Organization(s):

CALIFORNIA UNIV DAVIS INTEGRATED CIRCUITS LAB

Supplementary Note:

This article is from 'Proceedings of the International Symposium on Multiple-Valued Logic (13th) Held at Kyoto, Japan on May 23-25, 1983,' AD-A136 457, p190-195.

Pagination:

0006

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:

Approved For Public Release

RECORD

Collection: TR

Subject Terms

Communities of Interest:

Materials and Manufacturing Processes

Descriptor(s):

*Coders, *Decoders, *Silicon, *Logic circuits, *Complementary metal oxide semiconductors, Gates(Circuits), Parameters, Value, Electric current, Input, Output, Value, Coupling(Interaction), Binary notation

Keyword(s):

Component Reports, Multiple valued logic, Quaternary notation, Binary to quaternary concoders, Quaternary to binary concoders, Polysilicon gates, Concoder circuits, Encoding

Report Date:

1983 May 01