High Speed Parallel Backplane.

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Abstract:

This invention relates to high speed data processing in particular to a high speed parallel backplane for interconnecting a plurality of printed circuit boards in a parallel processing system. The conventional approach to parallel backplane design utilizes a set of circuit board connectors mounted on a flat supporting structure typically made of phenolic glass-epoxy. Common bus pins are interconnected via a set of linear metallized traces deposited on the supporting structure. Although this technique is acceptable for systems supporting low bandwidth exceeds 15 MHz. Of all the physical parameters which affect bus bandwidth, signal path length is the most crucial. According to the law of electromagnetics, when a signal path length approaches a quarter wavelength of operating frequency, radiative losses occur.

Author(s):
Corda, Albert J.
Author Organization(s):
DEPARTMENT OF THE NAVY WASHINGTON DC
Descriptive Note:
Patent application, filed 29 Jan 90,
Pagination:
0011

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
PAT-APPL-471 314
 Subject Terms
Communities of Interest:
No COI(s) Identified
Descriptor(s):
BANDWIDTH, CIRCUIT BOARDS, CONNECTORS, DATA PROCESSING, ELECTROMAGNETIC FIELDS, EPOXY COMPOUNDS, GLASS, HIGH RATE, LENGTH, LOSSES, METALLIZING, PARALLEL PROCESSING, PATHS, PHENOLS, PHYSICAL PROPERTIES, PINS, PRINTED CIRCUIT BOARDS, PROCESSING, RADIATION, SIGNALS
Field(s)/Group(s):
Computer Programming and Software
Keyword(s):
Patent applications, *Data processing, *Computers
Report Date:
1990 Jan 29