Parallel Neural Network for a Full Binary Adder.

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Abstract:

A method for performing the addition of two N-bit binary numbers using parallel neutral networks. The value of a first register is converted and transferred into a second register in a mathematical fashion so as to add the numbers of the first register into the second register. When the first register contains all zeros then the desired sum is found in the second register.

Author(s):
Johnson, John L.
Author Organization(s):
DEPARTMENT OF THE ARMY WASHINGTON DC
Descriptive Note:
Patent Application, Filed 17 Dec 87,
Pagination:
0011

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
PAT-APPL-135 404
 Subject Terms
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*NEURAL NETS, *PATENT APPLICATIONS, *REGISTERS(CIRCUITS), *BINARY PROCESSORS, PARALLEL ORIENTATION
Field(s)/Group(s):
Electrical and Electronic Equipment, Computer Hardware
Report Date:
1987 Dec 17