Data Buffer Circuit.

The subject invention overcomes some of the disadvantages of the prior art, including those mentioned above, in that it comprises a relatively simple data buffer circuit adapted for temporarily storing therein data which is to be processed by a computer. Included in the subject invention is a first input terminal adapted for receiving a data ready pulse signal, and a second input terminal adapted for receiving a data acknowledge pulse signal. First gating means, in response to the aforesaid data ready pulse signal, provides first, second, and third signals while second gating means, in response to the aforementioned data acknowledge pulse signal, provides first, second, and third select signals. First storage means will, in response to the first latch signal, store therein for a first predetermined time period a first sixteen-bit data word, and then transfer to the output thereof, in response to the first select signal, the aforementioned first sixteen-bit data word. Similarly, second storage means will, in response to the second latch signal, store therein for a second predetermined time period a second sixteen-bit data word, and then transfer to the output thereof, in response to the second select signal, the aforementioned second data word.