Multiple-Valued Logic Minimization for PLA Synthesis

reportActive / Technical Report | Accession Number: ADA606736 | Open PDF

Abstract:

Multiple-valued logic minimization is an important technique for reducing the area required by a Programmable Logic Array PLA. This report describes both heuristic and exact algorithms for solving the multiple-valued logic minimization problem. These algorithms have been implemented in a C program called Espresso-MV.

Author(s):
Rudell, Richard L.
Author Organization(s):
CALIFORNIA UNIV BERKELEY ELECTRONICS RESEARCH LAB
Descriptive Note:
Memorandum rept.
Supplementary Note:
DOI: 10.21236/ADA606736
Pagination:
0141

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
UCB/ERL-M86/65
Contract/Grant Number(s):
N00039-82-C-0107
Monitor Series:
DARPA
 Subject Terms
Joint Capability Areas:
JCA_5_Command and Control; JCA_5.3_Planning; JCA_1_Force Support; JCA_1.2_Force Preparation; JCA_1.2.5_Lessons Learned; JCA_5.5_Direct; JCA_5.5.1_Communicate Intent and Guidance; JCA_1.2.3_Educating; JCA_6.1.3_Switching and Routing; JCA_1.3_Human Capital Management; JCA_1.3.2_Personnel Management; JCA_6_Net Centric; JCA_6.1_Information Transport; JCA_8_Building Partnerships; JCA_1.2.6_Concepts; JCA_8.2_Shape
Communities of Interest:
Advanced Electronics
Descriptor(s):
*CODING, *LOGIC CIRCUITS, ALGORITHMS, LOGIC ELEMENTS, SPECIAL FUNCTIONS(MATHEMATICS)
Field(s)/Group(s):
Electrical and Electronic Equipment, Computer Programming and Software, Computer Hardware
Keyword(s):
LOGIC MINIMIZATION, LOGIC FUNCTIONS, BOOLEAN FUNCTIONS, PROGRAMMABLE LOGIC ARRAYS, CIRCUIT DESIGN
Report Date:
1986 Jun 05
Creation Date:
2014 Sep 17