Implementation of LPM Address Generators on FPGAs

We propose the multiple LUT cascade as a means to configure an eta-input LPM Longest Prefix Match address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n 32 and k 504 tilde 511. Also, we compare our design to a Xilinx proprietary TCAM ternary content-addressable memory design and to another design we propose as a likely solution to this problem. Our best multiple LUT cascade implementation has 5.20 times more throughput, 31.71 times more throughputarea and is 2.89 times more efficient in terms of area-delay product than Xilinxs proprietary design. Furthermore, its area is only 19 of Xilinxs design.