Efficient DSP Hardware Implementations for Navy RF Systems

The primary goal of this research was to investigate DSP hardware techniques to support the sharing of transmit hardware and array apertures between multiple simultaneous users of Navy RF Systems, specifically with respect to the implementation of delta-sigma converter based DSP systems. In particular, we considered 1 trade-offs between speed, space and power 2 finite precision analysis techniques to effect efficient hardware designs, and 3 algorithm and hardware considerations for critical path minimization. Specific investigations of candidate DSP architectures, including implementations in Xilinx FPGAs, allowed us to evaluate the performance of several alternate approaches.