Substrate Noise Coupling Analysis in 0.18 micrometer Silicon Germanium (SiGe) and Silicon on Insulator (SOI) Processes

Analysis of substrate noise coupling was performed for a 0.18 micrometer, lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as are methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to verify that the modeling approach used in simulation and the substrate noise model obtained using Silencer are accurate to within 10. The effects of a deep trench moat structure, bulk separation, and die perimeter ring also were tested as possible noise reduction methods. Strategies for simulation and measurement of substrate noise coupling in a 0.18 micrometer SOI process also are presented.