VHDL Modeling and Benchmarks

The MPL developed VHDL models for several commercial SRAMS, PROMS, and PLDs. A VHDL component library for use in simulating an X4000 FPGA implementation was created a netlist conversion tool is used for converting from a Xilinx LCA netlist format to a VHDL structural model. A SRAM VHDL model generator was created with an associated web browser interface that allowed SRAM VHDL models to be generated via the WWW. A VHDL intelligent tutor demonstration was done using Java and ActiveX capabilities coupled to the Microsoft Internet explorer Web Browser. The demonstration utilized materials from the SCRA VHDL Interactive Tutorial CDROM. The MPL developed a synthesizeable 1750A VHDL model based on the Fairchild F9450 implementation. The 1750A model included all 1750A instructions except for floating point, optional IO operations, and most of the console mode operations. The model was synthesized to both a standard cell netlist and a Xilinx X4000 netlist.