Designing Fast Golay Encoder/Decorder in Xilinx XACT With Mentor Graphics CAD Interface

The programmable logic array is one of the most fascinating and fast developing areas of technology. Field programmable gate arrays are becoming prevalent in design as the density of the gate arrays goes up. In this thesis study, a fast encodingdecoding algorithm, Extended Golay Coding, is implemented in Xilinx XC4000 family programmable gate array FPGA architecture. The encoderdecoder is designed using the Xilinx XACT tool with the Mentor Graphics schematic capture Design Architect DA and Quicksimll simulation interfaces. With the static RAM bits onboard the new Xilinx FPGAs, the architecture is more powerful, and it is relatively easy to upgrade the old design based on the needs of the users. In this thesis, fast encoderdecoder is implemented with transmission word redundancy and interleaving. This is based on the data link layer description of the Misted 181-144A. The FPGA static RAM bits are used for the encode and decode ROM of the algorithm that makes the coder faster. Modular approach and design hierarchy made design tasks easier and upgradable in this study. The timing simulations of some design modules will be presented. Due to the complexity of the circuits, it is found that the design has to be migrated to a higher density chip than X04003 used in the simulations.