A Scalable Video Rate Camera Interface

reportActive / Technical Report | Accession Number: ADA286144 | Open PDF

Abstract:

We survey the state of the art in high-speed interfaces for video input to high performance computers and note the difficulty of providing video at rates appropriate to modern parallel computers. Most interfaces that have been developed to date are not scalable, required extensive hardware development, and impose a full frame time delay between the moment the camera captures video and the moment it is available for processing. We propose a solution, based on a simple interface we have developed, which has been integrated into the iWarp parallel computer developed by Carnegie Mellon University and Intel Corporation. The interface takes advantage of iWarps systolic capabilities, does not impose any frame buffer delay time, was simple to design, and is readily scalable to provide up to 32 camera ports, from all of which data can be captured at full video rate, on a system that fits in a 19 6U rack. We have applied the system to multibaseline stereo vision, and provide performance figures. C.1.2 Multiple-instruction-stream, Multiple-data stream processors, Parallel processors, C.3 Real-time systems, 1.2.10 Vision and scene understanding, 1.2.9 Robotics, 1.3.1 Input devices, 1.4.1 Digitization, 1.4.2 Compression.

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release, Document Partially Illegible
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited. Document Partially Illegible.

RECORD

Collection: TR
Identifying Numbers
Subject Terms