A Pipelined, High-Precision FFT Architecture

reportActive / Technical Report | Accession Number: ADA257235 | Open PDF

Abstract:

This paper presents a highly-integrated, high-precision FFT architecture. A 1.2 um CMOS implementation of this architecture has yielded a 32-bit, 64K-point FFT that operates at a continuous 4-million-samples-per-second data rate. All FFT support functions, including coefficient generation and memory interfacing, are included on-chip. FFT architecture, CMOS implementation.

Author(s):
Hopkinson, Thomas M. ; Butler, G. M.
Author Organization(s):
MITRE CORP BEDFORD MA
Supplementary Note:
DOI: 10.21236/ADA257235
Pagination:
0021

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
MTP92B0000004
Contract/Grant Number(s):
F19628-89-C-0001
Monitor Series:
ESC*
 Subject Terms
Joint Capability Areas:
JCA_6_Net Centric; JCA_6.1_Information Transport; JCA_1.4.2_Health Service Delivery; JCA_1.4_Force Support; JCA_8_Building Partnerships
Modernization Areas:
Microelectronics
Communities of Interest:
Energy and Power Technologies
Descriptor(s):
*COMPUTER ARCHITECTURE, *FAST FOURIER TRANSFORMS, FUNCTIONS, COEFFICIENTS, ARCHITECTURE, PAPER, DATA RATE, PRECISION, RATES
Field(s)/Group(s):
Computer Hardware
Report Date:
1992 Oct 01