An Analysis of Aliasing in Built-In Self Test Procedure

reportActive / Technical Report | Accession Number: ADA246905 | Open PDF

Abstract:

This thesis investigates aliasing probability in Built-in Self Test BIST procedure, in which a Linear Feedback Shift Register LFSR is used as pseudo-random pattern generator, with a full adder as Circuit Under Test CUT. The Signature Analyzer implements a Multiple Input Signature Register MISR as a test response compressor.

Author(s):
Barus, Jasa
Author Organization(s):
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Descriptive Note:
Master's thesis,
Pagination:
0080

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Monitor Series:
NPS
 Subject Terms
Joint Capability Areas:
JCA_5_Command and Control; JCA_5.3_Planning; JCA_6.1.1_Wired Transmission; JCA_6.1_Information Transport; JCA_6_Net Centric; JCA_1.2.7_Experimentation; JCA_5.3.3_Develop Strategy; JCA_1_Force Support; JCA_1.2.5_Lessons Learned; JCA_1.2_Force Preparation; JCA_4.6_Engineering; JCA_5.5.2_Task; JCA_5.5_Direct
Modernization Areas:
Microelectronics
Communities of Interest:
Materials and Manufacturing Processes
Descriptor(s):
*TEST AND EVALUATION, TEST METHODS, THESES, RESPONSE, FEEDBACK, SHIFT REGISTERS, SELF OPERATION, SIGNATURES, COMPRESSORS, ANALYZERS, PSEUDO RANDOM SYSTEMS, PATTERN MAKING, LINEAR SYSTEMS, SELF CONTAINED
Field(s)/Group(s):
Electrical and Electronic Equipment
Keyword(s):
*CIRCUIT TESTERS, *SELF OPERATION, *PSEUDO RANDOM SEQUENCES, BIST(BUILT IN SELF TEST), THESES, SIGNATURES, INTEGRATED CIRCUITS, VERY LARGE SCALE INTEGRATION
Report Date:
1991 Jun 01