Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects

This final report describes progress made by TIS Incorporated for the period 7191 - 10191 toward the development of novel optical computer architectures and supporting methods for exploiting free-space reconfigurable interconnects. Major findings include 1 Reconfigurable interconnects can reconfigure slower than the bit rate and still improve performance as long as throughput is maintained after reconfiguration 2 A fixed control sequence does not preclude the use of runtime conditionals, so that the performance of traditional general purpose computing can be improved 3 A system that uses reconfigurable interconnects is likely to be larger than a functionally equivalent system that does not use reconfigurable interconnects 4 A reconfigurable approach is most effective for a small active portion of a computer, and is not needed for an entire computer in order to appreciate a performance gain 5 A reconfigurable interconnect technology can have a significant impact on interconnection networks used in parallel processors 6 A fixed control sequence must have some level of repetition in order to be practical and 7 The dataflow model of computing, which theoretically supports maximum parallelism but suffers performance sacrifices in electronic implementations, may be significantly improved since the architecture can be modified to suit the dataflow graph.