Netlist +: A Simple Interface Language for Chip Design

NetList is a design specification language developed at MOSIS for rapid turn-around cell-based ASIC prototyping. By using NetList , a uniform representation is achieved for the specification, simulation, and physical description of a design. Our goal is to establish an interfacing methodology between design specification and independent computer aided design tools. Designers need only to specify a system by writing a corresponding netlist. This netlist is used for both functional simulation and timing simulation. The same netlist is also used to derive the low level physical tools to generate layout. Another goal of using NetList is to generate parts of a design by running it through different kinds of placement and routing PR tools. For example some parts of a design will be generated by standard cell PR tools. Other parts may be generated by a layout tiler -- i.e. datapath compiler, RAMROM generator, or PLA generator. Finally all different parts of a design can be integrated by general block PR tools as a single chip. The NetList language can actually act as an interface among tools. Section 2 shows a flowchart to illustrate the NetList system and its relation with other related design tools. Section 3 shows how to write a NetList description from the block diagram of a circuit. In section 4 discusses how to prepare a cell library or several cell libraries for a design system. Section 5 gives a few designs by NetList and shows their simulation and layout results in the appendix.