Floating Gate Circuits in MOSIS
Abstract:
The MOSIS foundry offers a two-poly CMOS process that can be used as a floating gate technology, albeit not with the same performance as commercial EEPROM foundries. This report characterizes the structures and programming techniques necessary to build floating gate structures and associated high-voltage addressing circuitry on the low-noise analog process available through MOSIS. Techniques that are used include Fowler-Nordheim tunneling, channel hot-electron injection, and avalanche injection. The dielectric materials between the floating gate and both the control gate and substrate are characterized. Unconventional lightly doped drain FET devices and additional circuit techniques for handling the high-voltage programming signals are presented. Author