An Experiment on Intermittent-Failure Mechanisms.

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Abstract:

Intermittent failures are studied by stressing temperature, supply voltage and extra loading good parts. The behavior of the chips under stress is similar to that of a marginal chip under normal operating conditions. The experiments show that most intermittent failures are pattern-sensitive for both sequential and combinational circuits. The stuck-at fault model is shown to be inappropriate to describe intermittent failures. This paper presents a case where a single intermittent failure is not detected by a test set with 100 single stuck-at fault coverage. A stress-strength analysis is presented to explain the experimental results. Keywords Intermittent failures, Pattern sensitive faults, Soft failures, Integrated circuit reliability, Intermittent fault model.

Author(s):
Cortes, Mario L. ; Mccluskey, Edward J.
Author Organization(s):
STANFORD UNIV CA CENTER FOR RELIABLE COMPUTING
Descriptive Note:
Technical rept.,
Pagination:
0043

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
CRC-TR-87-7, CSL-TR-87-322
Contract/Grant Number(s):
N00014-85-K-0600
 Subject Terms
Joint Capability Areas:
JCA_5.3_Planning; JCA_5_Command and Control; JCA_1.2.7_Experimentation; JCA_1.2.5_Lessons Learned; JCA_1.3.2_Personnel Management
Modernization Areas:
Microelectronics
Communities of Interest:
Energy and Power Technologies
Descriptor(s):
*CHIPS(ELECTRONICS), *FAULTS, *FAILURE, *INTEGRATED CIRCUITS, BEHAVIOR, MODELS, RELIABILITY, PATTERNS, SENSITIVITY, TEST SETS
Field(s)/Group(s):
Computer Systems, Electrical and Electronic Equipment
Report Date:
1987 Mar 01