A Communication Bandwidth Model for Shuffle-Exchange and Augmented Shuffle-Exchange Interprocessor Communication Networks.

A failure dependent bandwidth model for shuffle exchange SE and augmented shuffle exchange SE interconnection networks is presented. The models are based on probabilities of either data or address mode failures for the individual binary switches which comprise the SE or SE network. The model gives the expected bandwidth as a function of the probability of failures in these switches. The model, which is consistent with those previously published when the probability of failure is zero, is first developed for the SE network. This model is extended to the SE network by developing a special model for the input stage of the SE network and then proving that, to within a close approximation, the conditions necessary for the SE model hold at the outputs of first stage of the SE. The model is verified using a computer simulation. An example is presented which demonstrates use of the model to predict the effects of several fault tolerance schemes on the bandwidth of these networks. The model demonstrates that, when used as a reliability enhancement, the extra stage of the SE causes a reduction in bandwidth as compared to an SE network.