Bulk CMOS VLSI Technology Studies. Part 5. The Design and Implementation of a High Speed Integrated Circuit Functional Tester.

This thesis project discusses the design and implementation of a functional tester to be used in a university laboratory facility for integrated circuit development. The following tester capabilities were desired 1 100KHz - 10 MHz Test Frequency, 2 2K x 64Bit Test Vector Size, 3 Four User Programmable Clocks, 4 Tesst Vector Input using High-Level Language, and 5 Test Data Manipulation Using a High-Level Language. The functional tester receives test vector data from a Hewlett Packard HP9920A computer and loads this data into functional tester buffer memory. After the data is down-loaded, including certain operational information such as a test clock frequency, programmable clock waveform information, data direction control, etc., the tester initiates the test using random-logic control circuitry to achieve the desired high speeds. The random-logic control circuitry indicates the completion of the test, at which time the resultant data, stored in buffer memory, is up-loaded to the HP9920A for processing. This design approach to a functional tester for laboratory use differs from--and improves upon-- previous methods, in that random-logic control circuitry is used during the test phase to provide greater operating speeds than systems which use microprocessor-control for the complete test.