Universal Pin Electronics.

reportActive / Technical Report | Accession Number: ADA126660 | Open PDF

Abstract:

The report describes a unique and advanced test system architecture which has the ability to put virtually an entire test system into a test head and is capable of operating at repetition rates of 100MHz and with test vectors of 250,000 bits deep. In addition, this new architecture has the potential to also provide extended analog capability with greatly improved reliability in a small physical package and at a reduced cost over conventional automatic test equipments. Block diagrams of the overall system, major subsystem and the single channel are presented and described. Specifications of the overall system and the single channel are also presented. In addition to its use as an off-line ATE, this architecture can bring its inherent testing power directly to built-in-test BIT applications. Author

Author(s):
Jackson, Philip C.
Author Organization(s):
GIORDANO ASSOCIATES INC SPARTA NJ
Descriptive Note:
Final rept. Aug 81-Sep 82,
Pagination:
0136

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
CECOM-81-0146-F
Contract/Grant Number(s):
DAAK80-81-C-0146
Task Number(s):
01
Project Number(s):
1L162746A094
Monitor Series:
81-0146-F
 Subject Terms
Joint Capability Areas:
JCA_5_Command and Control; JCA_6.1.3_Switching and Routing; JCA_6_Net Centric; JCA_6.1.1_Wired Transmission; JCA_5.5_Direct; JCA_5.5.1_Communicate Intent and Guidance; JCA_6.1_Information Transport; JCA_5.4.5_Intuit; JCA_5.4_Decide; JCA_5.3_Planning; JCA_1_Force Support; JCA_1.2_Force Preparation; JCA_1.2.6_Concepts; JCA_6.3.3_Spectrum Management; JCA_4.2_Supply; JCA_6.2.1_Information Sharing; JCA_6.2.2_Computing Services; JCA_1.2.5_Lessons Learned; JCA_4.2.3_Manage Global Supplier Networks; JCA_5.3.4_Develop Courses of Action; JCA_5.3.5_Analyze Courses of Action
Modernization Areas:
5G
Communities of Interest:
Energy and Power Technologies
Descriptor(s):
*DIGITAL SYSTEMS, *TEST EQUIPMENT, *PINS, COMPUTER PROGRAMS, ELECTRONICS, SYSTEMS ENGINEERING, REDUCTION, COSTS, RECEIVERS, CALIBRATION, FLOW CHARTING, ARCHITECTURE, ANALOG TO DIGITAL CONVERTERS, AUTOMATIC, ANALOG SYSTEMS, CHANNELS, DIGITAL TO ANALOG CONVERTERS
Field(s)/Group(s):
Computer Programming and Software, Computer Hardware, Test Facilities, Equipment and Methods
Keyword(s):
ATE(Automatic Test Equipment), Parametric signals, BIT(Built in Tests), Drivers, UPE(Universal Pin Electronics), Compacted words, Local memories, Self tests, Decompaction, Pin electronics, System buses, Buffers, PE62746A, AS094, WU012
Report Date:
1982 Nov 03