Wafer Scale Integration of Parallel Processors.

This research examines the problem of construction chips up to the size of the wafer wafer scale integration that operate correctly despite the occurrence of such flaws. We concentrate on a particular family of parallel processors, configurable, highly parallel CHiP processors. The key problem in the implementation of wafer scale integration is structuring the wafer so that only the functional PEs are connected together. A methodology, the two-level hierarchy, that efficiently and economically solves the structuring problem for CHiP processors is presented. The principle elements are the use of column exclusion with high yield building blocks that contain redundant components. This approach limits the performance degradation due to structuring and allows the structuring problem to be solved with tractable computational effort. Since the yield of building blocks must be high for the two-level hierarchy to be a practical approach, yield phenomena are investigated in detail.