Demonstration of the Use of VLSI Design Rules, Standards, and Interfaces

reportActive / Technical Report | Accession Number: ADA100583 | Open PDF

Abstract:

Topics reported include Task 1--Consultation from fabrication lines, CMOS-SOS and NMOS-Si gate test-chips, Geometrical design rules, Speed and timing rules, and Testability rules and Task 2--CIFAPPLICON, CALMA conversion software, and Circuit design.

Author(s):
Mead, Carver
Author Organization(s):
CALIFORNIA INST OF TECH PASADENA
Descriptive Note:
Research and development status rept. 1 Jun-1 Sep 1980
Supplementary Note:
DOI: 10.21236/ADA100583
Pagination:
0006

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Contract/Grant Number(s):
N00014-79-C-0924, ARPA ORDER-3771
Monitor Series:
DARPA
 Subject Terms
Joint Capability Areas:
JCA_4.6.1_General Engineering; JCA_4.6_Engineering; JCA_5_Command and Control; JCA_5.5.2_Task; JCA_5.5_Direct
Modernization Areas:
Microelectronics
Communities of Interest:
Advanced Electronics
Descriptor(s):
*INTEGRATED CIRCUITS, *STANDARDS, CHIPS(ELECTRONICS), COMPLEMENTARY METAL OXIDE SEMICONDUCTORS, FABRICATION, PROTOTYPES, SPECIFICATIONS, TEST EQUIPMENT
Field(s)/Group(s):
Electrical and Electronic Equipment
Keyword(s):
VLSI(Very Large Scale Integration), Silicon on sapphire, Circuit Design
Report Date:
1980 Sep 01