Microcomputer Array Processor.

The objective of this work was to design, fabricate, and bench test a feasibility model of an EW computer architecture based on utilizing multiple microprocessors in a multiprocessor system. The developed model consists of four microprocessors integrated into a tightly coupled nearly symmetrical structure exhibiting a master-slave relationship among its processors. Each microprocessor is composed of a 32-bit CPU and a dedicated local program memory. The function of the multiprocessor is to sort pulse trains based on digital pulse intercepts collected by a wide-open channelized receiver. Once the multiprocessor determines the PRI of an emitter, all emitter parameters are passed to a preprocessor which is inserted in the data stream between the receiver and the multiprocessor. The function of the preprocessor is to remove from the data stream all pulses from emitters identified by the multiprocessor. The feasibility model preprocessor can accept a peak receiver output pulse rate of 340,000 pulses per second.