Short Channel MOS for CCD Readout Circuit.

Wafer processing techniques have been developed to allow fabricating an n-MOS clamp-sample-and-hold CSH circuit suitable for detecting outputs from charge couple device shift registers operating at 25 MHz. The techniques developed include methods to define circa 1 micrometers device features using electron beam lithography as well as the methods of wafer processing to make functional MOSFET devices at these dimensions. In addition, the CSH circuit was designed and thoroughly simulated with computer models. The development work required determining techniques to etch fine structures in thin films of silicon nitride and polycrystalline silicon. Data were also obtained of the amount of underoxidation when a silicon wafer is oxidized using silicon nitride masking features. Methods were also developed to provide 400 A gate oxides, shallow np junctions, and reliable contacts to these junctions without metallization spiking. Several diagnostic chips were designed and fabricated. Experience with these provided a list of design rules for the fabrication, in general, of circuits using the high resolution nitride masked oxidation process. It also provided a list of device performance parameters. Author