A Virtual Memory System for the PDP-10 KA10 Processor.

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Abstract:

This report describes the development of the Large Space Virtual Memory System for operation with a Digital Equipment Corporation PDP-10 Computer system. The virtual memory system modifies the KA10 instruction set and addressing mechanisms to provide a virtual memory address space of 2 to the 36th power 36-bit words. Each address consists of a 9 bit segment number and a 27 bit within segment address. The VM control programs are based on a new page replacement algorithm, the Page Fault Frequency PFF Replacement Algorithm, called the Shared PFF SPFF. Author

Author(s):
Mcnamee, L. P.
Author Organization(s):
CALIFORNIA UNIV LOS ANGELES DEPT OF COMPUTER SCIENCE
Descriptive Note:
Final technical rept. Jul 75-Mar 76,
Pagination:
0098

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
RADC-TR-76-178
Contract/Grant Number(s):
F30602-74-C-0016
Task Number(s):
459410
Project Number(s):
AF-4594
Monitor Series:
TR-76-178
 Subject Terms
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*COMPUTER PROGRAMMING, *MEMORY DEVICES, *DIGITAL COMPUTERS, COMPUTER PROGRAMS, COMPUTER PROGRAM DOCUMENTATION, ALGORITHMS, INTERFACES, FORTRAN, MACROPROGRAMMING, INFORMATION SCIENCES, ADDRESSING
Field(s)/Group(s):
Computer Programming and Software, Computer Hardware
Keyword(s):
Virtual memories, PDP 10 computers, User manuals, Computer software
Report Date:
1976 Jun 01