Automation Feasibility Study for Microelectronic Wafer and Integrated Circuit Test Set, TTU-311/E.

The report describes an investigation of the feasibility of automating the microelectronic wafer and integrated circuit IC test set which was designed as an operator aid for the internal visual inspection of ICs. The theoretical limits to IC defect enhancement by single-element intensity spatial filtering as implemented in the test set are explored an alternative filtering technique array filtering with potentially higher signal defect to noise IC ratio is also treated. The engineering tradeoffs made in the design of the test set are found to substantially affect automation feasibility, and additional test set limitations are discussed. It is concluded that, while automation of the test set is straightforward one subsystem for automation is described in detail, the inherent limitations of single-element array filtering and the further specific details of the present test set cause immediate automation of the test set to be of doubtful value. A program is recommended to furhter evaluate the array filtering technique.