Design of a Memristive Dynamic Adaptive Neural Network Array (MRDANNA)

The objective of this effort was to build affordable, manufacturable, low power, dynamic neuromorphic computing platform for handling spiky, highly variable informationdata, as well as develop a low-power, hybrid memristorCMOS neuron synapse implementation for implementation of a hardware-based dynamic neural network array. The approach was to leverage hybrid CMOSmemristor encryption project to design, fabricate, and test memristorCMOS neurons synapses, and integrate them with existing FPGA implementations for full-scale dynamic neural network array demonstration. In addition, to make a module design kit library available for other circuits and architectures, thus making advancements in this effort useful to future designs that utilize hybrid CMOSmemristor technologies.