Interoperability and Cold-Spare Support for VLSI ICs Using a System-in-Package I/O Kit

VLSI ICs using sub-100 nm CMOS technology provide high speed and low power relative to larger geometry technology. However, at voltages above the breakdown voltage of individual 10 transistors, cold-spare support and interoperability with heritage IO standards are problematic. A System-in-Package SiP methodology leveraging BAE Systems family of radiation-hardened by design RHBD IO chiplets simplifies VLSI IC design while supporting 3.3 V IO and cold-spare operation. The SiP methodology and chiplets described support multiple technology nodes from 90 nm to at least 7 nm. Tristate IO, Flash memory interface and ANSIVita 78 Space VPX applications illustrate use of the IO chiplets.