Full Custom Integrated Circuit (IC) Design Flow at U.S. Army Research Laboratory

reportActive / Technical Report | Accession Number: AD1043295 | Open PDF

Abstract:

The steps required to set up and run the Cadence Full Custom Integrated Circuit Design Flow are given in detail. Included is a walkthrough showing the design of an inverter, from schematic capture through layout, including design rule check DRC, layout versus schematic LVS and parasitic extraction.

Author(s):
Wilson, James
Author Organization(s):
US Army Research Laboratory Adelphi United States
Descriptive Note:
Technical Report
Pagination:
0028

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release;

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
ARL-TN-0422
Monitor Series:
ARL-TN-0422
 Subject Terms
Joint Capability Areas:
JCA_5_Command and Control; JCA_6.1.3_Switching and Routing; JCA_6_Net Centric; JCA_6.1.1_Wired Transmission; JCA_6.1_Information Transport; JCA_3.2_Engagement; JCA_3_Force Application; JCA_3.2.1_Kinetic Means; JCA_8_Building Partnerships
Modernization Areas:
Microelectronics
Communities of Interest:
Advanced Electronics
Descriptor(s):
Integrated Circuits, radio frequency, software tools, simulations
Field(s)/Group(s):
Electrical and Electronic Equipment, Computer Programming and Software
Keyword(s):
Design flow, cadence, tutorial, drc(design rule check), lvs(layout versus schematic), pdk(process design kit)
Report Date:
2011 Feb 01
Creation Date:
2018 Feb 08