Wide Band Analog Multiplier.

The report covers the efforts performed during the 10 month design fabrication and test phase of the Analog Multiplier contract. During the design period, alternate operational amplifier designs were tested for use in the final multiplier. The results of these tests and the preferred design is described. The important characteristics of the field-effect transistors FET for use in the balanced bridge are discussed and a method of matching these devices in the bridge configuration is described. Two prototype multipliers were assembled and tested. After successful tests were conducted of the two prototype multipliers, 20 hybrid multipliers were assembled and final evaluation tests conducted. The test results are included as part of this report. Author