Design of a Secure Communications Processor: Central Processor,

reportActive / Technical Report | Accession Number: AD0781182 | Need Help?

Abstract:

The Secure Communications Processor is intended as a feasibility model for use in testing and verifying work concerned with the design and certification of secure access controls for computer systems. The system was conceived to be hardware independent, but is implemented on an Intercomputer Communications Corporation i-50 communications processor. The report, the third containing the design details, discusses the Central Processor Pc, half of the dual processor message switch. This volume contains implementation details of the access control and special instructions for the firmware and software requiring certification as well as operating concepts and a Users Manual for constructing the uncertified routines for Pc. Author

Author(s):
Tasker, P. S.
Author Organization(s):
MITRE CORP BEDFORD MASS
Supplementary Note:
See also Volume 1, AD-761 804.
Pagination:
0098

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
MTR-2439-Vol-3, ESD-TR-74-181
Contract/Grant Number(s):
F19628-73-C-0001
Project Number(s):
AF-7210
Monitor Series:
TR-74-181
 Subject Terms
Joint Capability Areas:
JCA_6.1.3_Switching and Routing; JCA_6.1_Information Transport; JCA_6_Net Centric; JCA_1.2_Force Preparation; JCA_1_Force Support
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*DATA PROCESSING SECURITY, *CENTRAL PROCESSING UNITS, *COMMUNICATIONS NETWORKS, MEMORY DEVICES, SWITCHING CIRCUITS, COMPUTER PROGRAMMING, NETWORK FLOWS
Field(s)/Group(s):
Computer Programming and Software, Computer Hardware, Computer Systems, Computer Systems Management and Standards
Keyword(s):
Computer networks, IC i 50 communications processors, Routing, Computer information security
Report Date:
1974 Jun 01